Computer Organization and Architecture
(COMP-ORG-ARC.AB1)
/ ISBN: 978-1-61691-838-5
This course includes
Lessons
TestPrep
Lab
Mentoring (Add-on)
Computer Organization and Architecture
The Computer Organization and Architecture course and lab cover the entire field of computer design updated with the most recent research and innovations in computer structure and function. The lab is cloud-based, device-enabled, and can easily be integrated with an LMS. The computer architecture course and lab also provides knowledge on the areas such as I/O functions and structures, RISC, and parallel processors with real-world examples enhancing the text for reader interest.
Lessons
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29+ Lessons
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200+ Quizzes
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176+ Flashcards
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176+ Glossary of terms
TestPrep
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50+ Pre Assessment Questions
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50+ Post Assessment Questions
Lab
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34+ Performance lab
- What’s New in the Eleventh Edition
- Support of ACM/IEEE Computer Science and Computer Engineering Curricula
- Objectives
- Example Systems
- Plan of the Text
- Organization and Architecture
- Structure and Function
- The IAS Computer
- Gates, Memory Cells, Chips, and Multichip Modules
- The Evolution of the Intel x86 Architecture
- Embedded Systems
- ARM Architecture
- Designing for Performance
- Multicore, Mics, and GPGPUs
- Two Laws that Provide Insight: Amdahl's Law and Little’s Law
- Basic Measures of Computer Performance
- Calculating the Mean
- Benchmarks and Spec
- Computer Components
- Computer Function
- Interconnection Structures
- Bus Interconnection
- Point-to-Point Interconnect
- PCI Express
- Principle of Locality
- Characteristics of Memory Systems
- The Memory Hierarchy
- Performance Modeling Of A Multilevel Memory Hierarchy
- Cache Memory Principles
- Elements of Cache Design
- Intel x86 Cache Organization
- The IBM z13 Cache Organization
- Cache Performance Models
- Semiconductor Main Memory
- Error Correction
- DDR DRAM
- eDRAM
- Flash Memory
- Newer Nonvolatile Solid-State Memory Technologies
- Magnetic Disk
- RAID
- Solid State Drives
- Optical Memory
- Magnetic Tape
- External Devices
- I/O Modules
- Programmed I/O
- Interrupt-Driven I/O
- Direct Memory Access
- Direct Cache Access
- I/O Channels and Processors
- External Interconnection Standards
- IBM z13 I/O Structure
- Operating System Overview
- Scheduling
- Memory Management
- Intel x86 Memory Management
- ARM Memory Management
- The Decimal System
- Positional Number Systems
- The Binary System
- Converting Between Binary and Decimal
- Hexadecimal Notation
- The Arithmetic and Logic Unit
- Integer Representation
- Integer Arithmetic
- Floating-Point Representation
- Floating-Point Arithmetic
- Boolean Algebra
- Gates
- Combinational Circuits
- Sequential Circuits
- Programmable Logic Devices
- Machine Instruction Characteristics
- Types of Operands
- Intel x86 and ARM Data Types
- Types of Operations
- Intel x86 and ARM Operation Types
- Appendix 13A Little-, Big-, and Bi-Endian
- Addressing Modes
- x86 and ARM Addressing Modes
- Instruction Formats
- x86 and ARM Instruction Formats
- Assembly Language Concepts
- Motivation For Assembly Language Programming
- Assembly Language Elements
- EXAMPLES
- Types of assemblers
- Assemblers
- Loading and Linking
- Processor Organization
- Register Organization
- Instruction Cycle
- Instruction Pipelining
- Processor Organization for Pipelining
- The x86 Processor Family
- The ARM Processor
- Instruction Execution Characteristics
- The Use of a Large Register File
- Compiler-Based Register Optimization
- Reduced Instruction Set Architecture
- RISC Pipelining
- MIPS R4000
- SPARC
- Processor Organization For Pipelining
- CISC, RISC, And Contemporary Systems
- Overview
- Design Issues
- Intel Core Microarchitecture
- ARM Cortex-A8
- ARM Cortex-M3
- Micro-Operations
- Control of the Processor
- Hardwired Implementation
- Microprogrammed Control
- Multiple Processor Organizations
- Symmetric Multiprocessors
- Cache Coherence and the MESI Protocol
- Multithreading and Chip Multiprocessors
- Clusters
- Nonuniform Memory Access
- Hardware Performance Issues
- Software Performance Issues
- Multicore Organization
- Heterogeneous Multicore Organization
- INTEL Core i7-5960X
- ARM Cortex-A15 MPCore
- IBM z13 Mainframe
- A.1 Bus Structure
- A.2 Multiple-Bus Hierarchies
- A.3 Elements of Bus Design
- B.1 Victim Cache
- B.2 Selective Victim Cache
- E.1 Stacks
- E.2 Stack Implementation
- E.3 Expression Evaluation
- F.1 Recursion
- F.2 Activation Tree Representation
- F.3 Stack Implementation
- F.4 Recursion And Iteration
- G.1 Pipeline Reservation Tables
- G.2 Reorder Buffers
- G.3 Tomasulo’s Algorithm
- G.4 Scoreboarding
Hands on Activities (Performance Labs)
- Installing Expansion Cards on a Motherboard
- Supplying Power to a SATA Drive
- Providing Cooling and Ventilation to a Motherboard
- Installing Motherboard Components
- Replacing the Battery of a Smartphone and Inserting a Memory Card
- Calculating the Mean
- Assembling Computer Components
- Installing a USB 3.0 PCI Express Card (2.0 x4)
- Determining the Characteristics of Memory Devices in a Memory Architecture
- Determining L3 Cache Sizes for The Processors
- Determining Semiconductor Memory Types and Their Erasure Processes
- Connecting the Motherboard to the Internal Hard Drive
- Inserting a CD on a Laptop
- Connecting a Keyboard, Mouse, and Monitor to a Computer
- Installing a NIC
- Connecting a workstation to the Ethernet and to the Internet
- Connecting the Hub with Different Devices Using USB Cables
- Installing FireWire Cards
- Configuring a Wireless Client
- Converting Fraction Decimal Number into Equivalent Binary Number
- Converting Decimal Number into Two's Complement Binary Number
- Identifying Types of Logic Gates
- Changing the Resolution Settings
- Identify the Addressing Mode
- Using Greatest Common Divisor
- Installing a Processor
- Determining Characteristics of Processors
- Understanding the Intel Core Microarchitecture
- Understanding The Functioning of Microprogrammed Control Unit
- Determing the Types of Parallel Processor Systems
- Installing Memory Modules
- Identifying Chip Organizations
- Identifying Levels of Cache
- Determining ARM ACE Cache Line States
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